(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a smooth gate polysilicon sidewall in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, photolithography and etching are used to form structures such as polysilicon gates, local oxidation of silicon (LOCOS), shallow trench isolation (STI), and the like. The photoresist material is coated over the layer or layers to be etched. The photoresist is exposed to actinic light through a mask, then developed to form the photoresist mask for etching the underlying layer or layers.
Polysilicon is used as the gate electrode of MOS transistors. The gate electrode is fabricated by reactive ion etching of the polysilicon with the pattern defined by the photoresist mask. Using the current art, the sidewall of the polysilicon after etching is rough. The roughness is determined by the grain size of the polysilicon crystals at the time of etching. For ultrasmall geometry devices the grain size becomes comparable to the device line widths. This may lead to poor polysilicon critical dimension (CD) distribution after etch which in turn affects the control of parameters such as threshold voltage (V.sub.t) and drain saturation current (I.sub.dsat). Use of amorphous silicon for the gate material instead of polysilicon results in smoother sidewalls due to the absence of grains. This solution, however, results in an increase in undesirable polysilicon depletion effects causing higher gate oxide capacitance and higher threshold voltage.
U.S. Pat. No. 5,393,682 to Liu teaches a method of damaging a polysilicon layer, then using an anisotropic etch to more quickly remove the damaged layer. The result is a tapered, trapezoidal shaped gate structure rather than a rectangular gate. U.S. Pat. No. 5,731,239 to Wong et al teaches a method using a pre-amorphizing implantation resulting in smaller grain sizes. U.S. Pat. No. 5,548,132 to Batra et al teaches a method using an amorphizing silicon implant affecting grain sizes in polysilicon. U.S. Pat. No. 5,652,156 to Laio et al teaches a method of forming the gate using multiple layers of polysilicon and amorphized silicon.